In general, a synchronous memory device such as DDR SDRAM uses a DLL circuit, which is an internal clock generation circuit used for synchronizing an external clock from an outside source to output data.
Specifically, when a clock input from outside of a memory device is used as an internal clock for the memory device, the clock's propagation through internal circuitry will cause a time delay. A DLL circuit controls or compensates for propagation delay such that internal and external clocks can have the same phase. More accurately, a DLL circuit is used for outputting data by synchronizing output data to an external clock.
FIG. 1 is an example of a typical prior art DLL circuit. Clock buffers 111 and 112 are internal buffers for receiving external clocks /CLK and CLK. Here, the clock signal /CLK is an inverted signal of the clock signal CLK. The clock signals /CLK and CLK passed through each of the clock buffers 111 and 112 are indicated by internal clock signals fclkt2 and rclkt2.
A delay line 113 receives the internal clock signal fclkt2 and delays the internal clock signal for a predetermined period of time. Delay line 114 receives the internal clock signal rclkt2 and delays the internal clock signal rclkts for a predetermined period of time. For reference, delay times of the delay lines 113 and 114 are varied by a delay line controller 117 as will be described later.
A replica delay unit 115 for receiving an output signal of the delay line 114, is a delay unit having a fixed delay time, which nearly coincides with the sum of a delay time t1 of the clock buffer 111 and a delay time t2 of a DLL driver 118.
A phase comparator 116 compares a phase of the internal clock signal rclkt2, which is an output signal of the buffer 112, with a phase of an output signal fb_clk of the replica delay unit 115.
The delay line controller 117 controls the delay times of the delay lines 113 and 114 in response to an output signal of the phase comparator 116.
DLL drivers 118 and 119 receive the output signals of the delay lines 113 and 114 to output internal DLL signals fclk_dll and rclk_dll.
When the phases of signals rclkt2 and fb_clk applied to the phase comparator 116 coincide, the locking of the DLL circuit is made. That is, the delay time of the delay lines 113 and 114 controlled by the delay line controller 117 will be fixed.
Such a DLL circuit will be placed into an enable state when a memory device is in normal operation mode, but an operation of the DLL circuit needs to be blocked while the memory device maintains power-down mode to reduce the power consumption.
Conventionally, a method of blocking an operation of the buffer 111 at power-down mode has been used. That is, when the memory device enters into power-down mode, the buffer 111 is disabled by using an inverted signal Ckeb of a clock enable signal Cke to reduce the power consumed in the DLL circuit.
Of course, it is preferable that the buffer 111 and the buffer 112 are both disabled to greatly reduce the power consumed in the DLL circuit at power-down mode.
However, when the buffer 112 is disabled at power down mode and the buffer 112 is enabled upon exiting from power-down mode, a problem usually follows.
When the buffer 112 is enabled upon exiting from power-down mode, the internal clock signal rclkt2 is immediately applied to the phase comparator 116, but the output signal fb_clk of the replica delay unit, which is a feedback signal, is applied after a predetermined time period (after the total delay time of the delay line 114 and the replica delay unit 115 has passed). Due to this, the phase comparator 116 will make a wrong decision, and the DLL locking time will be also lengthened.
For this reason, conventionally, the buffer 112 should be maintained in an enable state even at power-down mode. As a result there has been a problem that the power comsumed in the DLL circuit even at power-down mode is above a specified level.